Li Yixuan shook his head and denied: "The memory chip is now fighting hard between the United States and Japan, and I am not interested in getting involved, the chip I produce is a management and control chip for hard disks, which is a small branch of industrial control chips." ”

"Oh, industrial control chips, can you tell us more specifically?" As the director of the Department of Industry, Guo Yingnian certainly knew about industrial control chips, but he didn't expect Li Yixuan to actually produce this, but he never believed that the other party wanted to produce industrial control chips, thinking that Li Yixuan was fooling him.

Of course Li Yixuan is fooling him, he will definitely do it on the desktop CPU, and he must do it, but does he dare to say that, once he says so, does he expect the other party to approve the land for industrial use, and bluff the other party first.

Guide the other party to a hard disk assembly area, pick up the circuit board from the assembly line, "Director Guo, please see, the chip on this circuit board is an industrial control chip, this is the 65C02 processor released by Western Digital in the United States, and what I want to produce is the CPU that can replace it." ”

"65C02, what does this have to do with the 6502CPU produced by Huake?" Guo Yingnian keenly felt that there should be a great relationship between the two.

In 1974, Chuck Peder brought six engineers from Motorola to found MOS Technology, one of the six engineers named bill mensch (Bill Mens), he was very ambitious, after MOS Technology completed the development of the 6502 processor, quickly saw the opportunity, from MOS Technology, founded western design center, i.e., the Western Design Center.

Finally, in 1978, Bill successfully developed the 65C02 processor based on the CMOS process, and successfully realized the cross-generation upgrade of the 6502 processor. Although the 65C02 is better than the 6502, it is a commercial failure, the 6502 only costs $25, while each 65C02 costs $128, such a high price, the performance is not comparable to Intel's 8086 and 8087 processors.

As a result, Bill Mens had to revise the design, and although the cost was reduced, the performance was also greatly reduced, and more importantly, in the low-end processor market, the Western Design Center had lost its lead, and he had been firmly occupied by MOS.

As a last resort, the Western Design Center can only develop into embedded processors and provide industrial control solutions for IBM's hard disks and 8-inch floppy drives. A blessing in disguise, WDC has been a great success in this field. That's why my hard drive uses 65C02 as the control chip. ”

Guo Yingnian didn't know that the two companies still had such a relationship, and asked, "Then why don't you continue to use 65C02?"

"Because 65C02 has great shortcomings, its control logic core relies on the ROM chip on the interface control card, which occupies a large DMA channel, which makes the design of the hard disk circuit control board complicated, and the area of the circuit board is also very large. Director Guo, you see, the circuit board in front of you is almost stained with one side of the entire hard disk, and it is impossible to make the hard disk smaller.

In addition, he also affected the upgrade of the hard disk capacity, 10MB capacity is fine, the capacity is 20MB, and the performance of 65C02 cannot be supported. What's more, due to the 65C02's own control logic, users have to endure a lot of jumpers and toggle switches during the use of the hard disk (in the early days of computers, the system resources occupied by each device were allocated by the user manually changing the jumper or toggle switch), which brought difficulties to the ease of use of the hard disk.

So I'm going to change it and redesign a new type of controller chip to make the hard drive convenient and easy to use. ”

Guo Yingnian was stunned by the various professional terms that popped out of Li Yixuan's mouth, but he still grabbed a key word from the other party sharply, "Do you know how to design chips?"

“YES。 Li Yixuan replied calmly.

Now Guo Yingnian is not calm, you must know that chip design is a high-tech job, there is no company in Hong Kong that knows how to design chips, even Huake Electronics Industry Co., Ltd. can't, its 6502 chips are imported from MOS, how the other party designs, how to produce themselves, even a small modification can not be done, and the young man in front of him actually said that he can design chips, so he really can't believe it.

Li Yixuan knew that the other party couldn't believe it just by saying it, so he took out the sketch of the chip he designed, he was not afraid of being leaked, because he had already applied for a patent for this kind of architecture design, and an overall design sketch couldn't explain anything.

Spread out the drawings, and a preliminary design sketch of the CPU was presented in front of Guo Yingnian's eyes.

The chip designed by Li Yixuan adopts the common ARM processor structure in later generations, and the Harvard pipeline structure used by ARM, which is a common structure used by most RISC reduced instruction set processors.

Of course, due to the different design priorities, the Harvard assembly line structure evolved into many different structures. The core design concept of ARM is low power consumption and low cost, which is stable and reliable. Later, it became the preferred CPU for mobile electronic devices, and later the hard disk control CPU, whether it is a traditional mechanical hard disk or a solid state drive, or a portable mobile hard disk, the control chip on it is a variant of the ARM processor.

ARM was developed in 1983 by Acorn Computer (the predecessor of ARM) in the United Kingdom, with the aim of developing a new architecture with low power consumption and low power consumption, and full compatibility with the 6502 processor on the market.

In 1975, MOS Technology released the 6502 processor, based on which Acorn developed an Acorn educational computer, which was later designated as a specialized computer by the British government's educational institutions, which made Acorn a smash hit in the mid-to-late seventies in the United Kingdom.

But as time went on, the 6502 CPU, which was then high performance and low price, was gradually falling behind the times, and Acorn needed to launch a new computer, that is, a 16-bit computer.

However, Acorn sadly found that MOS Technology did not have the idea of launching a new generation of 16-bit processors, they just changed the original 8-bit processor 6502 on the basis of the 6502, from 6502 to 6504, to 6507, and then to 6600, which is still only an improved version of the 6502, which is not the processor that Acorn wants at all.

In 1980, the two companies negotiated and MOS Technology agreed to develop a 16-bit processor, the 7520, for Acorn, which was the last processor developed by MOS Technology.

What makes Acorn sad is that the 7520 is not compatible with the 6502 at all, which makes it impossible for Acorn to develop various applications around the 6502 to continue to be used on the new computer, and the British educational institutions are even more reluctant to invalidate the previous applications.

This is not a misguided child, how can the British educational institutions agree.

In the end, Acorn had no choice but to spend $3 million to buy a full set of 6502 technology licenses from MOS Technology to design a new 16-bit processor that was fully compatible with the 6502 processor.

At this time, the world's first real RISC processor MIPS was born, and the birth of MIPS shook the entire semiconductor industry, and many industry experts believe that RISC will be the next generation of processors, which will eventually replace CISC complex instruction set processors. In fact, we all know that CISC has not been replaced by RISC, and it is still alive and well.

As a result, Acorn began to change its design thinking and design a reduced instruction set CPU that was fully compatible with 6502, namely the Acorn RISC Machine processor, which was the predecessor of the ARM processor.

In fact, it can be seen from here that ARM is very different from MIPS, it is not a pure RISC, it has a lot of CISC only functional expansibility characteristics, and the function expansion ability is still very strong, which is why the later ARM company can design so many ARM series processors with different functions based on the ARM architecture, not to mention that there are countless variants of ARM processors.

Li Yixuan will not say these secrets in the history of processor development to Guo Yingnian, and it has not happened yet, with Li Yixuan, an intruder, he can't be sure whether this matter will happen or not, and now he just needs to convince Guo Yingnian.

The ARM processor started as 32-bit, and the most familiar thing we are with is the 64-bit structure of ARM, which is only 79 years old now, and it cannot be copied directly.

Li Yixuan has changed it, and the 16-bit ARM processor consists of an instruction register module, an arithmetic operation unit, a microprocessor controller module, a program counter, a subroutine counter module, a data memory module, and a data bus processor module.

These devices are also described in the lower right corner of the drawing.

1: The instruction register module mainly completes the acceptance of instruction words from read-only memory (ROM), and at the same time distributes the instruction words to the control component and the internal data bus or address bus. Because the current design is a 16-bit processor, after receiving the 16-bit instruction word, the high 8-bit opcode is sent to the control module for decoding the instruction through the control signal sent by the microprocessor controller, and the data and address of the lower 8-bit are sent to the address bus or data bus.

2: The program counter module is designed with a 16-bit program counter, and must also be able to directly accept the jump address.

3: The subroutine counter module itself is also equivalent to a program counter, which is set by the control signal generated by the controller in the processor, and once the number is set, it is the start address of the subprogram. In addition, the subroutine counter is also a program counter that can mask interrupts and non-maskable interrupt the execution process of the program, reducing the complexity of the program counter design.

4: The arithmetic logic unit module is the processor running arithmetic and logical operations, and there is also a register module associated with this module, the extensive use of registers is a distinctive feature of the RISC architecture, he is mainly used to store the two operands of the arithmetic logic operation, and it is also the storage component of the arithmetic logic unit operation results.

5: In order to be able to read data and write data from the data memory, the data memory module must have a storage address register and a storage data register to temporarily store the address and data to be stored.

6: The microprocessor control module gives the operation pulse signal of each module in different working states through the decoding of instructions, and is the brain of the entire microprocessor, which is composed of a decoder, a ring counter and a control matrix. Wherein the ring counter generates the control state required by the control matrix, and the instruction decoding and control matrix are realized by the control module.

7: The data bus processor module mainly solves the internal data bus conflict problem and responds to the bus requests of different modules.

This basically completes the structure of the general framework of the processor and the definition of the functions of each functional module. Li Yixuan does not need too high a high level of technological leadership, so he decided not to use the multiple access instruction format, for the total control chip used on the hard disk, the multiple access instruction is completely useless, and it will increase the addressing time of the instruction.

Li Yixuan designed a L2 cache system for the chip, Level 1 4K, Level 2 8K, which can greatly increase the read and write speed of the hard disk.

The design of the cache should not be too large or too low, and it must be appropriate according to the actual purpose of the chip. It's big, it's useless, not to mention the waste of cost, it's small and not enough, in short, as long as the hard disk capacity of this control chip does not exceed 2GB, it will not be eliminated.

This control CPU Li Yixuan also adopts a pipeline design, divided into user mode and dedicated mode 2 working modes, and registers are also divided into 2 kinds, general register and special register, for which 16 registers are specially designed, in user mode, instructions can only access 12 general registers, and dedicated mode can be accessed voluntarily by all 16 registers, from user mode to private mode The key is interrupt and exception.

For the data channel of the pipeline, there are only two cases, one is that the executed instruction code is invalid and needs to be transferred to the interrupt service program, and the other is the exception or interrupt instruction, such as system start, hardware interrupt, and interrupt return.

In Li Yixuan's design, the execution process of instructions is divided into three steps: taking instructions, decoding and executing.

First of all, let us see that for example, there are 3 instructions input into the computer is 123,123,123, then after the pipeline is adopted, the execution of the situation first takes the value of 1 and then decodes to the position of 2, at this time the second instruction just enters the value link, when the instruction 1 enters the execution stage, then the second instruction is just the decoding stage, and the third instruction is in the value stage, so that the processor will run at full speed inside, and the execution efficiency of the processor is the highest at this time, which is also a technology that can increase the performance of the computer without increasing the frequency of the computer。

Li Yixuan adopts a 3-level pipeline design, which can fully meet the current situation and the needs of the next 10 years of hard disk capacity growth, for a CPU for the total control of hard disks, there is no need to design any 4-level 5-level or even 8-level 9-level pipelines, you will not see the future 4TB capacity hard disk, and the assembly bus of its total control chip is only 10 levels.

On the contrary, in the design of the bus, Li Yixuan has spent a lot of brain cells, not only to meet the needs of the present, but also to meet the needs of the future.

The bus is the internal data, address and control signal transmission channel of the processor, and it is also the interface for external communication, so the design of the processor bus has a very important impact on the performance of the processor.

It's like if a city doesn't have wide, smooth and fast roads, compared to those with wide roads or even highways, if you want to get from the east of the city to the west of the city, you think it's faster.

Li Yixuan divides the off-chip bus into three parts: data bus, address bus and control bus, and adopts a three-bus parallel structure.

The data bus is a 16-bit bidirectional bus, which is used for external program memory or data memory to read instructions or data and external data memory to write channels, and the read-only memory and random memory reads and writes are time-sharing multiplexing. The address bus is also 16 bits, the addressable space is 64K, the program counter is a 16-bit address register, which is used to store the address of the program memory to be accessed, and the subroutine counter is also a 16-bit address register, which replaces the function of the program register when the subprogram calls or executes interrupt programs.

The external control bus will consist of read, write, and prepare signals to access the memory, mainly reading and writing external memory and I/O devices.

This is the external bus, followed by the internal bus structure. There are two design structures for the internal bus, which one to choose, Li Yixuan also thought about it for a long time.

What are the two bus structures?

Von Neumann system and Harvard system, naturally Harvard system is of great help to improve the performance of the computer, but it will also cause the complexity of the process and is not conducive to cost control, Harvard structure is a memory structure that separates program instruction storage and data storage.

The central processing unit first reads the program instruction content in the program instruction memory, obtains the data address after decoding, and then reads the data in the corresponding data memory, and proceeds to the next operation (usually execution).

The program instruction storage and data storage are separated, so that the instructions and data can have different data widths.

The von Neumann structure, also known as the Princeton structure, is a memory structure that combines program instruction memory and data memory together. The program instruction storage address and the data storage address point to different physical locations of the same memory, so the program instruction and data are the same width, and Intel's 8086 is this structure.

Li Yixuan later thought about it carefully, the biggest advantage of the memory of the Harvard architecture is that it facilitates the continuity of the subsequent design of the chip, and the disadvantage is that the process production is complicated, which is not conducive to cost control.

Although the internal bus structure of the ARM processor adopts the Harvard system, the current CPU is used as the main control chip of the hard disk. For hard drives, there is no need to think too much about the continuity of the future internal bus design, as long as it can meet the original design requirements, and in the end he chose the von Neumann structure.

Even if Li Yixuan's speech was in-depth and concise, so that ordinary people could understand it as much as possible, it was a pity that Guo Yingnian still didn't understand.

No way, the CPU is too professional. He's just a bureaucrat, not an expert in his field, but that doesn't matter to him, the important thing is that he now knows that the young man in front of him can really design chips.

The balance in Guo Yingnian's heart began to tilt, but he still had a question, "I believe you can design chips now, but where do you get the production line?"