Regarding the dying struggles of Shin-Etsu and LG Chem, Huang Haojie didn't care.

Because for Galaxy Technology, the area of silicon wafers has lost its meaning.

If needed, Neutron Star can produce large-area square wafers at any time, so even if Shin-Etsu and LG Chem develop 18-inch wafers, it will not help.

Neutron Star Materials' square wafers are leading the wafer wafers in an all-round way, which is an unstoppable trend, and their dying struggle is just a mantis arm as a car.

Now Huang Haojie is in the semiconductor research institute of Galaxy Technology.

More than 100 graduates majoring in semiconductors recruited by Galaxy Technology itself, plus five engineers or researchers poached from domestic semiconductor companies, plus more than a dozen engineers and researchers brought by Zhang Rujing.

Although there are only more than 100 people in the semiconductor research institute of Galaxy Technology, although the sparrow is small, it has all kinds of organs.

Huang Haojie looked at the methodical semiconductor research institute and nodded with satisfaction.

"Li Xiang, how are you doing about the mechanism of C31 transporting other chip materials?"

Li Xiang lifted his glasses and replied with a little excitement: "This C31 fullerene can handle most of the raw materials for making chips, and even if a small part of the other parts cannot be handled, we can also use the raw materials that can be transported to replace them." ”

"Very good."

"Boss, I think this invention of yours can win the dynamite prize." A Mediterranean researcher was amazed.

"What about the Dynamite Award? I don't need this kind of thing. "Huang Haojie is not a real professional background, and he doesn't care too much about things like the explosives award.

…… The researchers and engineers were speechless and choked, others wanted to win the dynamite award, but their boss was good and didn't care at all.

Huang Haojie and a group of engineers are developing a chip manufacturing process that is different from the current chip process.

Generally speaking, chip factories buy silicon wafers directly from wafer factories and do not produce them themselves.

The chip manufacturing plant will first inspect the silicon wafer, and after checking that there is no damage, it can be put into the production line, and there may be various film-forming processes in the early stage, and then it will enter the photoresist application link.

Microlithography is a graphic photocopying technology and a key process in the integrated circuit manufacturing process.

First, a photoresist (photosensitive resin) is dropped onto a silicon wafer, evenly coated into a photoresist film by high-speed rotation, and the photoresist film is applied to cure at an appropriate temperature.

Photoresist is a material that is very sensitive to light, temperature and humidity, and can change its chemical properties after exposure to light, which is the basis of the entire process.

Next up is UV exposure.

In terms of individual technical processes, the lithography process is the most complex and the most costly.

Because the lithography template, lens, and light source together determine the size of the transistor "imprinted" on the photoresist.

The photoresist-coated wafer is placed into the exposure device of the stepper repeater to "copy" the mask pattern.

There is a pre-designed circuit pattern in the mask, and the ultraviolet light passes through the mask and is refracted by a special lens to form the circuit pattern in the mask on the photoresist layer.

Generally speaking, the circuit pattern obtained on the silicon wafer is 1/10, 1/5, and 1/4 of the pattern on the mask, so the step repeat exposure machine is also called "reduced projection exposure device".

There are two major factors that determine the performance of a step-by-step repeat exposure machine: one is the wavelength of the light, and the other is the numerical aperture of the lens.

If you want to reduce the size of the transistors on a silicon wafer, you need to look for a lens with a shorter wavelength (EUV, extreme ultraviolet light) that can be used reasonably, and a lens with a larger numerical aperture (there are limits depending on the lens material).

Part of the photoresist is dissolved, and the exposed silicon wafer is developed.

Taking positive photoresist as an example, after spraying a strong alkaline developer, the photoresist irradiated by ultraviolet light will undergo a chemical reaction, and a chemical reaction will occur under the action of alkali solution, and it will be dissolved in the developer, while the unirradiated photoresist pattern will be intact.

After the development, the surface of the silicon wafer is rinsed, sent to the oven for heat treatment, evaporation of water and curing of the photoresist.

Then it goes to the etching stage.

By immersing the wafer in a special etching tank containing an etching agent, the exposed wafer is dissolved, while the remaining photoresist protects the part that does not need to be etched.

During this period, ultrasonic vibration is applied to accelerate the removal of impurities attached to the surface of the silicon wafer and prevent the etching products from staying on the surface of the silicon wafer and causing uneven etching.

The next step is to remove the photoresist.

The photoresist is ashed by oxygen plasma to remove all photoresist.

At this point, the first layer of the designed circuit pattern can be completed.

Repeat steps 6-8, since the current transistors have been designed with 3D FinFETs, it is impossible to produce the required graphics at one time, and steps 6-8 need to be repeated for processing, and various film-forming processes (insulating film, metal film) will be involved in the process to obtain the final 3D transistor.

This is followed by the ion implantation stage.

The process of consciously introducing specific impurities into a specific area is called "impurity diffusion".

In addition to controlling the type of conductivity (P-junction, N-junction), impurity diffusion can also be used to control the concentration and distribution of impurities.

In the ion implanter, the conductive impurities that need to be doped are introduced into the arc chamber, ionized by discharge, and after the electric field is accelerated, the ion beam of tens to thousands of keV energy is injected from the surface of the silicon wafer.

After ion implantation, the silicon wafer also needs to undergo heat treatment, which on the one hand uses the principle of thermal diffusion to further "press" impurities into the silicon, and on the other hand, restores the integrity of the crystal lattice and activates the electrical properties of impurities.

Ion implantation has the advantages of low processing temperature, uniform and large-area injection of impurities, and easy control, so it has become an indispensable process in VLSI circuits.

Remove the photoresist again. After ion implantation, the photoresist mask left over from selective doping can be removed.

At this point, a small fraction of the silicon atoms inside the monocrystalline silicon have been replaced with "impurity" elements, resulting in free electrons or holes.

Insulating layer treatment, at this time, the prototype of the transistor has been basically completed, and the vapor deposition method is used to comprehensively deposit a layer of silicon oxide film on the surface of the silicon wafer to form an insulating layer.

Photolithography is also used to make holes in the interlayer insulating film in order to elimigrate the conductor electrodes.

Precipitate the copper layer, use the sputtering deposition method to deposit the copper layer for wiring on the entire surface of the silicon wafer, and continue to use photolithography mask technology to engrave the copper layer to form the source, drain and gate of the FET.

Finally, an insulating layer is deposited on the entire surface of the silicon wafer to protect the transistor.

Construct the connection circuit between transistors.

After a long process, billions of transistors have been made.

All that's left is the question of how to connect these transistors.

The same is to form a layer of copper first, and then delicate operations such as photolithography masks, etching holes, etching holes, and then deposit the next layer of copper.

This process is repeated many times, depending on the size of the transistors of the chip and the degree of replication.

The result is an extremely complex network of multi-layer connected circuits.

Because the IC now contains a variety of fine components and a huge interconnection circuit, the structure is very complex, the actual circuit layer has been as high as 30 layers, the surface of various uneven more and more, the height difference is very large, so the development of CMP chemical mechanical polishing technology.

CMP grinding is performed for each completed circuit.

In addition, in order to successfully complete the multi-layer Cu three-dimensional wiring, a new wiring method of the Damascus method was developed, in which the blocking metal layer was plated, the overall Cu film was sputtered, and then the Cu and blocking metal layers outside the wiring were removed by CMP to form the required wiring.

The chip circuit has been basically completed so far, which has gone through hundreds of different processes, and all of them are based on refined operations, any mistake will lead to the scrapping of the entire silicon wafer, and billions of transistors are manufactured on a silicon wafer of more than 100 square millimeters, which is the crystallization of all the wisdom of human civilization since civilization.

And it is so complicated, hundreds of processes are just to carve the lines on the silicon wafer, inject conductive impurities, and form a switch.